Japanese Patent Laid-open No. 2011-129816 (Patent Literature 1) discloses a conventional memory cell (refer to FIG. 15 in Patent Literature 1) in which a memory gate structure is disposed between two select gate structures. This memory cell includes a drain region connected with a bit line, a source region connected with a source line, and a first select gate structure, a memory gate structure, and a second select gate structure sequentially disposed on the memory well between the drain and source regions. In the memory cell with this configuration, the memory gate structure is provided with a charge storage layer. Data is programmed by injecting charge into the charge storage layer, and erased by removing charge from the charge storage layer.
In such a memory cell, when charge is injected into the charge storage layer, the second select gate structure connected with the source line blocks voltage application, whereas a low bit voltage from the bit line is applied to a channel layer below the memory gate structure through the first select gate structure. In this case, a high memory gate voltage is applied to a memory gate electrode of the memory gate structure, and charge is injected into the charge storage layer by a quantum tunneling effect due to a voltage difference between the bit voltage and the memory gate voltage.